From: lkcl <lkcl@web>
Date: Sat, 2 Jul 2022 22:09:06 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1400
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94499950b4c3305c166c3aea0320050de53a302f;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index a6055f1d2..dd9d2846f 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -141,9 +141,7 @@ by SimpleV:
   (VSX Rijndael and SHA primitives; VSX shuffle and bitpermute operations)
 * register files above 128 entries
 * Vector lengths over 64
-* Unit-strided LD/ST and other comprehensive memory operations
-  (struct-based LD/ST from RVV for example)
-* 32-bit instruction lengths. [[svp64]] had to be added as 64 bit.
+* 32-bit instruction lengths. [[sv/svp64]] had to be added as 64 bit.
 
 These limitations, which stem inherently from the adaptation process of
 starting from a Scalar ISA, are not insurmountable. Over time, they may