From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 8 Nov 2018 18:11:43 +0000 (+0000)
Subject: zero-extend mulhu result
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9456213f9ea59177bd57e9a2a420e3d3ed99b13c;p=riscv-isa-sim.git

zero-extend mulhu result
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 67ced5e..dc3037c 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -619,7 +619,11 @@ sv_reg_t sv_proc_t::rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs)
                 (uint64_t)lhs, (uint64_t)rhs, (uint64_t)result);
         return result;
     }
-    uint64_t result = (vlhs * vrhs) >> std::min(bitwidth, (uint8_t)32);
+    uint8_t bw32 = std::min(bitwidth, (uint8_t)32);
+    uint64_t result = (vlhs * vrhs) >> bw32;
+    result = zext_bwid(result, bw32);
+    fprintf(stderr, "mulhu result %lx %lx %lx bw %d\n",
+            (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(result), bitwidth);
     return rv_int_op_finish(lhs, rhs, result, bitwidth);
 }
 
@@ -746,6 +750,8 @@ bool sv_proc_t::rv_eq(sv_reg_t const & lhs, sv_reg_t const & rhs)
 
 bool sv_proc_t::rv_ne(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
+    fprintf(stderr, "rv_ne %lx %lx %d\n",
+            (uint64_t)lhs, (uint64_t)rhs, (lhs != rhs));
     return (lhs != rhs);
 }