From: lkcl <lkcl@web>
Date: Thu, 9 Jun 2022 10:01:18 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1900
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=945ced0ef9cad91aab6a7c050aa7804015cba53f;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 0b967f366..423cb47b3 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -27,7 +27,8 @@ exempts element width overrides,
 which still do not actually modify the meaning of the instruction:
 an add remains an add, even if its override makes it an 8-bit add rather than
 a 64-bit add. Even add-with-carry remains an add-with-carry: it's just
-that when elwidth=8 in the Prefix it's an *8-bit* add-with-carry.
+that when elwidth=8 in the Prefix it's an *8-bit* add-with-carry,
+where the 9th bit becomes Carry-out, not the 65th bit.
 In other words, elwidth overrides **definitely** do not fundamentally
 alter the actual
 Scalar v3.0 ISA encoding itself.  Consequently we can still, in