From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 13:08:48 +0000 (+0200)
Subject: tools/litex_sim: use similar analyzer configuration than wiki.
X-Git-Tag: 24jan2021_ls180~430
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9460e048ec782900c3199ebded0e57128c8216ac;p=litex.git

tools/litex_sim: use similar analyzer configuration than wiki.
---

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 7a526f83..987681d3 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -270,10 +270,19 @@ class SimSoC(SoCSDRAM):
         # Analyzer ---------------------------------------------------------------------------------
         if with_analyzer:
             analyzer_signals = [
-                self.cpu.ibus,
-                self.cpu.dbus
+                self.cpu.ibus.stb,
+                self.cpu.ibus.cyc,
+                self.cpu.ibus.adr,
+                self.cpu.ibus.we,
+                self.cpu.ibus.ack,
+                self.cpu.ibus.sel,
+                self.cpu.ibus.dat_w,
+                self.cpu.ibus.dat_r,
             ]
-            self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
+            self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
+                depth        = 512,
+                clock_domain = "sys",
+                csr_csv      = "analyzer.csv")
             self.add_csr("analyzer")
 
 # Build --------------------------------------------------------------------------------------------