From: lkcl <lkcl@web>
Date: Sun, 12 Jun 2022 12:53:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1833
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9460eb92c21b2a90b19b9ca14af05ea14a408193;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 182e9bea6..80f3d08fe 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -114,10 +114,12 @@ Horizontal-First Mode:
   destinations.  Strict Program Order is required in full.
 
 *Implementor's note: the cost of Vertical-First Mode in an Embedded design
-of storing four 64-bit in-flight elements may be too high. If this is the
+of storing four 64-bit in-flight elements may be considered
+too high. If this is the
 case it is acceptable to throw an Illegal Instruction Trap, and emulate
 the instruction in software. Performance will obviously be adversely affected.
-See [[sv/compliancy_levels]]*
+See [[sv/compliancy_levels]]*: all aspects of
+Swizzle are entirely optional in hardware at the Embedded Level.
 
 # RM Mode Concept: