From: lkcl Date: Fri, 6 Aug 2021 10:24:44 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~482 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9462612fe9c3e36fc5bfbbe5ea6f92536f211261;p=libreriscv.git --- diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 5f1139315..c561baa47 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -98,8 +98,8 @@ SVP64 RM `MODE` (includes `ELWIDTH` and `ELWIDTH_SRC` bits) for Branch Condition | 4 | 5 | 6 | 7 | 19 | 20 | 21 | 22 23 | description | | - | - | - | - | -- | -- | --- |---------|-------------------------- | -|ALL|LRu|BRc| / | 0 | 0 | / | SNZ sz | normal mode | -|ALL|LRu|BRc| / | 0 | 1 | VLI | SNZ sz | VLSET mode | +|ALL|LRu| / | / | 0 | 0 | / | SNZ sz | normal mode | +|ALL|LRu| / | / | 0 | 1 | VLI | SNZ sz | VLSET mode | |ALL|LRu|BRc| / | 1 | 0 | / | SNZ sz | svstep mode | |ALL|LRu|BRc| / | 1 | 1 | VLI | SNZ sz | svstep+VLSET mode |