From: lkcl <lkcl@web>
Date: Mon, 2 May 2022 09:55:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2519
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=946580c30375c74f774d226d81679d594867f27a;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 4c6020b64..8a591abb3 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -416,7 +416,12 @@ is based on whether the number of src operands is 2 or 3.  With only
 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding)   |
 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding)   |
 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding)   |
-| EXTRA2_MODE   | `18`    | used by `msubed` and `madded` for RS   |
+| EXTRA2_MODE   | `18`    | used by `divmod2du` and `madded` for RS   |
+
+These are for 3 operand in and either 1 or 2 out instructions.
+3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
+such as `madded` have an implicit second destination, RS, the
+selection of which is determined by bit 18.
 
 ## RM-1P-2S1D