From: Luke Kenneth Casson Leighton Date: Thu, 3 May 2018 03:52:41 +0000 (+0100) Subject: add neel comments X-Git-Tag: convert-csv-opcode-to-binary~5384 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94673076a110f3783c8b90c955f3e5753566e256;p=libreriscv.git add neel comments --- diff --git a/isa_conflict_resolution/mvendor_march_mimplid.mdwn b/isa_conflict_resolution/mvendor_march_mimplid.mdwn index ae487a42b..25b5f8bda 100644 --- a/isa_conflict_resolution/mvendor_march_mimplid.mdwn +++ b/isa_conflict_resolution/mvendor_march_mimplid.mdwn @@ -44,6 +44,26 @@ document. This idea allows every hart (core) to have the ability to select any one of multiple ISA encodings, by setting mimpl *in U-mode*. +> I agree.. complete renumbering is a huge overhead. Guy's solution avoids +> that overhead and provides a fast-switching mechanism. We had already +> identified what happens on traps, flushes, caches, etc. Would prefer if +> we could review/critique that proposal. +> +> If someone wants to re-number the entire custom ISA even then Guy's +> solution will stand. Plus, in the heterogenous envrionemt, considering +> each hart/core has its own marcselect(mutable csr), the M mode (or +> user/supervisor) can simply choose to enable that hart/core by writing +> to the marchselect CSR. +> +> For compliance, yes we will need Jacob's idea of having a global database +> somewhere. Also, I believe that the compliance will check only if the +> core is RISC-V compliant and not worry about any other extensions present +> or not. +> +> By adding a new mutable csr in the MRW region even existing +> implementations will be compliant since accessing this CSR in current +> implementations would just trap. + ## Every hart, multiple ISA encodings, mimpl set to "default" on traps ## Every hart, multiple ISA encodings, mimpl set to "supervisor-selectable"