From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 Aug 2020 13:31:38 +0000 (+0100)
Subject: adding bus data width of 64 in litex sim doesnt work
X-Git-Tag: semi_working_ecp5~441^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=946a7abe63fbbd7e6dac7949ddd4fcad448ce877;p=soc.git

adding bus data width of 64 in litex sim doesnt work
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 7d883b91..4ecb3ad5 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -32,6 +32,7 @@ class LibreSoCSim(SoCCore):
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
+            #bus_data_width           = 64,
             uart_name                = "sim",
             integrated_rom_size      = 0x10000,
             integrated_main_ram_size = 0x10000000) # 256MB