From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Nov 2013 17:17:10 +0000 (+0100)
Subject: Renamed extend_un0() to extend_u0() and use it in genrtlil
X-Git-Tag: yosys-0.2.0~386
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=947bd9b96bb978e204275d6fbbc9ce9ff6eda28c;p=yosys.git

Renamed extend_un0() to extend_u0() and use it in genrtlil
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index e901a3b52..c701c2fa0 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -966,7 +966,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_TO_UNSIGNED: {
 			RTLIL::SigSpec sig = children[0]->genRTLIL();
 			if (sig.width < width_hint)
-				sig.extend(width_hint, sign_hint);
+				sig.extend_u0(width_hint, sign_hint);
 			is_signed = sign_hint;
 			return sig;
 	}
@@ -983,7 +983,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				}
 			}
 			if (sig.width < width_hint)
-				sig.extend(width_hint, false);
+				sig.extend_u0(width_hint, false);
 			return sig;
 		}
 
@@ -998,7 +998,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			for (int i = 0; i < count; i++)
 				sig.append(right);
 			if (sig.width < width_hint)
-				sig.extend(width_hint, false);
+				sig.extend_u0(width_hint, false);
 			is_signed = false;
 			return sig;
 		}
@@ -1153,7 +1153,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			widthExtend(this, val1, width, is_signed);
 			widthExtend(this, val2, width, is_signed);
 
-			return mux2rtlil(this, cond, val1, val2);
+			RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
+
+			if (sig.width < width_hint)
+				sig.extend_u0(width_hint, sign_hint);
+			return sig;
 		}
 
 	// generate $memrd cells for memory read ports
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 4388acb1d..d03fb0448 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -940,7 +940,7 @@ void RTLIL::SigSpec::extend(int width, bool is_signed)
 	optimize();
 }
 
-void RTLIL::SigSpec::extend_un0(int width, bool is_signed)
+void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 {
 	if (this->width > width)
 		remove(width, this->width - width);
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 376a09abf..7628bf0a8 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -342,7 +342,7 @@ struct RTLIL::SigSpec {
 	void append(const RTLIL::SigSpec &signal);
 	bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool override = false);
 	void extend(int width, bool is_signed = false);
-	void extend_un0(int width, bool is_signed = false);
+	void extend_u0(int width, bool is_signed = false);
 	void check() const;
 	bool operator <(const RTLIL::SigSpec &other) const;
 	bool operator ==(const RTLIL::SigSpec &other) const;
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index f20181f1e..b7b361e95 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -151,8 +151,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 			if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
 				int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
-				a.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
-				b.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
+				a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
+				b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
 			}
 
 			RTLIL::SigSpec new_a, new_b;