From: lkcl <lkcl@web>
Date: Mon, 16 Aug 2021 10:48:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~435
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=947e643a0948e563b6339acc8875180e28685395;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 337953a7b..1391cf8e3 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -315,3 +315,21 @@ loop:
       bne cr0, loop
     end:
       blr
+
+## setmvlhi double loop
+
+```
+   setmvlhi  8, 2 # MVL=8, VFHint=2
+loop:
+    setvl  r5, r3 # VL=r5=MAX(MVL, r3)
+loopinner:
+    sv.ld r20.v, r4(0) # load VLhint elements (max 2)
+    sv.addi r20.v, r20.v, 55 # add 55 to 2 elements
+    sv.st r20.v, r4(0) # store VLhint elements
+    svstep.            # srcstep += VLhint
+    bnz loopinner      # repeat until srcstep=VL
+    # now done VL elements, move to next batch
+    add r4, r4, r5 # move r4 pointer forward
+    sub. r3, r3, r5 # decrement total count by VL
+    bnz loop
+```