From: Florent Kermarrec Date: Tue, 2 Oct 2018 10:20:32 +0000 (+0200) Subject: cores/cpu: revert vexriscv (it seems there is a regression in last version) X-Git-Tag: 24jan2021_ls180~1573 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=948527b0fe8e4bfee8b5010dd8dc119655db2758;p=litex.git cores/cpu: revert vexriscv (it seems there is a regression in last version) --- diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index e8a30b95..395c5ee2 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit e8a30b95b9aa1445b5a4a76579a98a0552e2db53 +Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5 diff --git a/litex/soc/software/include/base/csr-defs.h b/litex/soc/software/include/base/csr-defs.h index d98e8dfb..5f5ea847 100644 --- a/litex/soc/software/include/base/csr-defs.h +++ b/litex/soc/software/include/base/csr-defs.h @@ -3,8 +3,8 @@ #define CSR_MSTATUS_MIE 0x8 -#define CSR_IRQ_MASK 0xBC0 -#define CSR_IRQ_PENDING 0xFC0 +#define CSR_IRQ_MASK 0x330 +#define CSR_IRQ_PENDING 0x360 #define CSR_DCACHE_INFO 0xCC0