From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 29 Jul 2020 14:15:35 +0000 (+0200)
Subject: Match SoC granularity with decoder granularity
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9485a47f9a677193b04a92bf593e1c83cf13f07d;p=gram.git

Match SoC granularity with decoder granularity
---

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index d086b91..2a96b3d 100644
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -25,7 +25,7 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
-        self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=32)
+        self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=8)
 
         tck = 2/(2*2*100e6)
         nphases = 2