From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 May 2020 09:56:28 +0000 (+0100)
Subject: update comments on condition register
X-Git-Tag: div_pipeline~1119
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9491aa84dc99b5372a03f601f5137b826ece8a39;p=soc.git

update comments on condition register
---

diff --git a/src/soc/cr/main_stage.py b/src/soc/cr/main_stage.py
index dea936a6..b3b2b44f 100644
--- a/src/soc/cr/main_stage.py
+++ b/src/soc/cr/main_stage.py
@@ -1,6 +1,7 @@
 # This stage is intended to do Condition Register instructions
 # and output, as well as carry and overflow generation.
-# NOTE: we really should be doing the field decoding which
+# NOTE: with the exception of mtcrf and mfcr, we really should be doing
+# the field decoding which
 # selects which bits of CR are to be read / written, back in the
 # decoder / insn-isue, have both self.i.cr and self.o.cr
 # be broken down into 4-bit-wide "registers", with their