From: Marek Olšák <marek.olsak@amd.com>
Date: Sun, 30 Jul 2017 14:41:39 +0000 (+0200)
Subject: radeonsi: set up HTILE in descriptors only when level 0 is accessible
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94965b8219508954a5fddd74e7c6de4503cd9931;p=mesa.git

radeonsi: set up HTILE in descriptors only when level 0 is accessible

Compression isn't enabled with non-zero levels.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 18b070ba3a2..b080562348c 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -432,7 +432,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 
 			if (sscreen->b.chip_class <= VI)
 				meta_va += base_level_info->dcc_offset;
-		} else if (tex->tc_compatible_htile) {
+		} else if (tex->tc_compatible_htile && first_level == 0) {
 			meta_va = tex->resource.gpu_address + tex->htile_offset;
 		}