From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 1 Jul 2020 06:35:54 +0000 (+0200)
Subject: boards/platforms/versa_ecp5: fix mising update.
X-Git-Tag: 24jan2021_ls180~123
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=949a8e73c29ce6575ba8d445c7c6238d8e0a7af4;p=litex.git

boards/platforms/versa_ecp5: fix mising update.
---

diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py
index 4ea3df46..4ab23830 100644
--- a/litex/boards/platforms/versa_ecp5.py
+++ b/litex/boards/platforms/versa_ecp5.py
@@ -221,8 +221,9 @@ class Platform(LatticePlatform):
     default_clk_name   = "clk100"
     default_clk_period = 1e9/100e6
 
-    def __init__(self, **kwargs):
-        LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
+    def __init__(self, device="LFE5UM5G", **kwargs):
+        assert device in ["LFE5UM5G", "LFE5UM"]
+        LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, **kwargs)
 
     def create_programmer(self):
         return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")