From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Fri, 30 Aug 2019 11:17:03 +0000 (+0300)
Subject: div_mod test fix
X-Git-Tag: working-ls180~1084^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94a56c14b78a2872d65bb30371151e934a259275;p=yosys.git

div_mod test fix
---

diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
index f55490572..21cac7144 100644
--- a/tests/ice40/div_mod.ys
+++ b/tests/ice40/div_mod.ys
@@ -5,5 +5,5 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 62 t:SB_LUT4
-select -assert-count 65 t:SB_CARRY
+select -assert-count 41 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D