From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 16 Jul 2020 10:06:04 +0000 (+0100)
Subject: sigh, bug in sprset.patch
X-Git-Tag: div_pipeline~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94a784159ee3e4a48d3d8e03528d9016bd262372;p=soc.git

sigh, bug in sprset.patch
---

diff --git a/src/soc/decoder/isa/sprset.patch b/src/soc/decoder/isa/sprset.patch
index edbe55dc..2a115ae2 100644
--- a/src/soc/decoder/isa/sprset.patch
+++ b/src/soc/decoder/isa/sprset.patch
@@ -24,9 +24,9 @@
      def op_setb(self, CR):
 -        if eq(CR[4 * BFA + 32], 1):
 +        if eq(CR.si[4 * BFA + 32], 1):
-             RT = SelectableInt(value=0xffffffffffffffff, bits=256)
+             RT = SelectableInt(value=0xffffffffffffffff, bits=64)
 -        elif eq(CR[4 * BFA + 33], 1):
 +        elif eq(CR.si[4 * BFA + 33], 1):
-             RT = SelectableInt(value=0x1, bits=256)
+             RT = SelectableInt(value=0x1, bits=64)
          else:
-             RT = SelectableInt(value=0x0, bits=256)
+             RT = SelectableInt(value=0x0, bits=64)