From: lkcl <lkcl@web>
Date: Thu, 9 Jun 2022 15:50:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1894
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94b519a28a6c533dcffbbb2d23919c9c91a06f98;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 93da4d218..b46b83bfb 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -256,7 +256,7 @@ The underlying key to understanding:
 
 # CR weird instructions
 
-[[sv/int_cr_predication]] is by far the biggest violator of the SVP64
+[[openpower/sv/int_cr_predication]] is by far the biggest violator of the SVP64
 rules, for good reasons.  Transfers between Vectors of CR Fields and Integers
 for use as predicates is very awkward without them.
 
@@ -279,7 +279,7 @@ ISA is anathematic. In a Traditional Vector ISA however, where the
 indices are isolated behind a single Vector Hazard, there is no
 problem at all.  `sv.mv.x` is also fraught, precisely because it
 sits on top of a Standard Scalar register paradigm, not a Vector
-ISA, with separate and distinct Vector registers.
+ISA with separate and distinct Vector registers.
 
 To help partly solve this, `sv.mv.x` would have had to have
 been made relative: