From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 3 Jul 2020 12:29:32 +0000 (+0200)
Subject: Fix autopep8 madness
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94b6f9f01a0878a4404ad2a7959abeb7709be977;p=gram.git

Fix autopep8 madness
---

diff --git a/contrib/simulation b/contrib/simulation
new file mode 100644
index 0000000..83f1922
--- /dev/null
+++ b/contrib/simulation
@@ -0,0 +1,2 @@
+cd gram/simulation
+time ./runsimcrg.sh
\ No newline at end of file
diff --git a/gram/dfii.py b/gram/dfii.py
index 34d85bc..53053fe 100644
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -61,12 +61,9 @@ class DFIInjector(Elaboratable):
     def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
         self._nranks = nranks
 
-        self._inti = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
-        self.slave = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
-        self.master = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
+        self._inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
 
         self._control = csr_bank.csr(4, "w")  # sel, cke, odt, reset_n