From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 19 May 2020 20:38:51 +0000 (+0100)
Subject: rename module, remove extraneous code and imports
X-Git-Tag: div_pipeline~1062
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94c8df0d6018db62979002d25faa21bfbf002eb1;p=soc.git

rename module, remove extraneous code and imports
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index c29ac0a8..9141a30d 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -1,7 +1,6 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed)
 from nmutil.pipemodbase import PipeModBase
-from nmutil.clz import CLZ
 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
 from soc.decoder.power_enums import InternalOp
 
@@ -9,14 +8,7 @@ from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
 
-def array_of(count, bitwidth):
-    res = []
-    for i in range(count):
-        res.append(Signal(bitwidth, reset_less=True))
-    return res
-
-
-class LogicalMainStage(PipeModBase):
+class TrapMainStage(PipeModBase):
     def __init__(self, pspec):
         super().__init__(pspec, "main")
         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])