From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Dec 2019 18:29:40 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/master' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~65
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94f15f023c8720d84211ac75980cf0b0f492411d;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_dff
---

94f15f023c8720d84211ac75980cf0b0f492411d
diff --cc techlibs/xilinx/cells_sim.v
index ef963793c,cf7923777..7941a94cd
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -312,15 -310,60 +312,50 @@@ module FDRE_1 
    (* abc9_arrival=303 *)
    output reg Q,
    (* clkbuf_sink *)
 -  (* invertible_pin = "IS_C_INVERTED" *)
    input C,
 -  input CE,
 -  (* invertible_pin = "IS_D_INVERTED" *)
 -  input D,
 -  (* invertible_pin = "IS_S_INVERTED" *)
 -  input S
 +  input CE, D, R
  );
 -  parameter [0:0] INIT = 1'b1;
 -  parameter [0:0] IS_C_INVERTED = 1'b0;
 -  parameter [0:0] IS_D_INVERTED = 1'b0;
 -  parameter [0:0] IS_S_INVERTED = 1'b0;
 +  parameter [0:0] INIT = 1'b0;
    initial Q <= INIT;
 -  generate case (|IS_C_INVERTED)
 -    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 -    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 -  endcase endgenerate
 +  always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
  endmodule
  
+ module FDRSE (
+   output reg Q,
+   (* clkbuf_sink *)
+   (* invertible_pin = "IS_C_INVERTED" *)
+   input C,
+   (* invertible_pin = "IS_CE_INVERTED" *)
+   input CE,
+   (* invertible_pin = "IS_D_INVERTED" *)
+   input D,
+   (* invertible_pin = "IS_R_INVERTED" *)
+   input R,
+   (* invertible_pin = "IS_S_INVERTED" *)
+   input S
+ );
+   parameter [0:0] INIT = 1'b0;
+   parameter [0:0] IS_C_INVERTED = 1'b0;
+   parameter [0:0] IS_CE_INVERTED = 1'b0;
+   parameter [0:0] IS_D_INVERTED = 1'b0;
+   parameter [0:0] IS_R_INVERTED = 1'b0;
+   parameter [0:0] IS_S_INVERTED = 1'b0;
+   initial Q <= INIT;
+   wire c = C ^ IS_C_INVERTED;
+   wire ce = CE ^ IS_CE_INVERTED;
+   wire d = D ^ IS_D_INVERTED;
+   wire r = R ^ IS_R_INVERTED;
+   wire s = S ^ IS_S_INVERTED;
+   always @(posedge c)
+     if (r)
+       Q <= 0;
+     else if (s)
+       Q <= 1;
+     else if (ce)
+       Q <= d;
+ endmodule
+ 
 +(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
  module FDCE (
    (* abc9_arrival=303 *)
    output reg Q,
diff --cc techlibs/xilinx/synth_xilinx.cc
index de262c8ad,971089b28..ac6fedc58
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -559,10 -564,14 +566,11 @@@ struct SynthXilinxPass : public ScriptP
  				run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
  			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
  			if (help_mode)
 -				techmap_args += " [-map " + ff_map_file + "]";
 -			else if (abc9)
 -				techmap_args += " -map +/xilinx/abc9_unmap.v";
 -			else
 -				techmap_args += " -map " + ff_map_file;
 -			run("techmap " + techmap_args);
 +				techmap_args += stringf("[-map %s]", ff_map_file.c_str());
 +			else if (!abc9)
 +				techmap_args += stringf(" -map %s", ff_map_file.c_str());
 +			run("techmap " + techmap_args, "(option without '-abc9')");
+ 			run("xilinx_dffopt");
 -			run("clean");
  		}
  
  		if (check_label("finalize")) {