From: Wilco Dijkstra Date: Mon, 14 Nov 2016 12:04:11 +0000 (+0000) Subject: Currently the SBFM, UBFM and BFM instructions all use the attribute "bfm". X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94f7a25eebd2599175e838f09afe7daf59c3e9c1;p=gcc.git Currently the SBFM, UBFM and BFM instructions all use the attribute "bfm". SBFM and UBFM include all shifts on AArch64, which are simpler than bitfield insert. Add a new bfx attribute for these instructions so that they can be modelled more accurately in the future. There is no difference in code generation. * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3) Use bfx attribute. (aarch64_lshr_sisd_or_int_3): Likewise. (aarch64_ashr_sisd_or_int_3): Likewise. (si3_insn_uxtw): Likewise. (3_insn): Likewise. (_ashl): Likewise. (zero_extend_lshr): Likewise. (extend_ashr): Likewise. (): Likewise. (insv): Likewise. (andim_ashift_bfiz): Likewise. * config/aarch64/thunderx.md (thunderx_shift): Add bfx. * config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise. * config/arm/cortex-a57.md (cortex_a57_alu): Add bfx. * config/arm/exynos-m1.md (exynos_m1_alu): Add bfx. (exynos_m1_alu_p): Likewise. * config/arm/types.md: Add bfx. * config/arm/xgene1.md (xgene1_bfm): Add bfx. From-SVN: r242384 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b3967a245de..07173ab54e8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2016-11-14 Wilco Dijkstra + + * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3) + Use bfx attribute. + (aarch64_lshr_sisd_or_int_3): Likewise. + (aarch64_ashr_sisd_or_int_3): Likewise. + (si3_insn_uxtw): Likewise. + (3_insn): Likewise. + (_ashl): Likewise. + (zero_extend_lshr): Likewise. + (extend_ashr): Likewise. + (): Likewise. + (insv): Likewise. + (andim_ashift_bfiz): Likewise. + * config/aarch64/thunderx.md (thunderx_shift): Add bfx. + * config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise. + * config/arm/cortex-a57.md (cortex_a57_alu): Add bfx. + * config/arm/exynos-m1.md (exynos_m1_alu): Add bfx. + (exynos_m1_alu_p): Likewise. + * config/arm/types.md: Add bfx. + * config/arm/xgene1.md (xgene1_bfm): Add bfx. + 2016-11-14 Wilco Dijkstra * config/aarch64/aarch64.c (cortexa57_vector_cost): diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 46eaa30b159..a652a7c12bd 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3955,7 +3955,7 @@ shl\t%0, %1, %2 ushl\t%0, %1, %2" [(set_attr "simd" "no,no,yes,yes") - (set_attr "type" "bfm,shift_reg,neon_shift_imm, neon_shift_reg")] + (set_attr "type" "bfx,shift_reg,neon_shift_imm, neon_shift_reg")] ) ;; Logical right shift using SISD or Integer instruction @@ -3972,7 +3972,7 @@ # #" [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfm,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + (set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] ) (define_split @@ -4019,7 +4019,7 @@ # #" [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfm,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + (set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] ) (define_split @@ -4129,7 +4129,7 @@ "@ \\t%w0, %w1, %2 \\t%w0, %w1, %w2" - [(set_attr "type" "bfm,shift_reg")] + [(set_attr "type" "bfx,shift_reg")] ) (define_insn "*3_insn" @@ -4141,7 +4141,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "\t%w0, %w1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) (define_insn "*extr5_insn" @@ -4234,7 +4234,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "bfiz\t%0, %1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) (define_insn "*zero_extend_lshr" @@ -4247,7 +4247,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "ubfx\t%0, %1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) (define_insn "*extend_ashr" @@ -4260,7 +4260,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "sbfx\\t%0, %1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) ;; ------------------------------------------------------------------- @@ -4292,7 +4292,7 @@ "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), 1, GET_MODE_BITSIZE (mode) - 1)" "bfx\\t%0, %1, %3, %2" - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) ;; Bitfield Insert (insv) @@ -4374,7 +4374,7 @@ : GEN_INT ( - UINTVAL (operands[2])); return "bfiz\t%0, %1, %2, %3"; } - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) ;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below @@ -4386,7 +4386,7 @@ (match_operand 3 "const_int_operand" "n")))] "aarch64_mask_and_shift_for_ubfiz_p (mode, operands[3], operands[2])" "ubfiz\\t%0, %1, %2, %P3" - [(set_attr "type" "bfm")] + [(set_attr "type" "bfx")] ) (define_insn "bswap2" diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index 058713a2ad9..7c1c28b0498 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -39,7 +39,7 @@ (define_insn_reservation "thunderx_shift" 1 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev")) + (eq_attr "type" "bfm,bfx,extend,rotate_imm,shift_imm,shift_reg,rbit,rev")) "thunderx_pipe0 | thunderx_pipe1") diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 70c0f4daabe..eb6d0b04976 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -93,7 +93,7 @@ (and (eq_attr "tune" "cortexa53") (eq_attr "type" "alu_shift_imm,alus_shift_imm, crc,logic_shift_imm,logics_shift_imm, - alu_ext,alus_ext,bfm,extend,mvn_shift")) + alu_ext,alus_ext,bfm,bfx,extend,mvn_shift")) "cortex_a53_slot_any") (define_insn_reservation "cortex_a53_alu_shift_reg" 3 diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index 85b18e5970f..da461846baa 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -297,7 +297,7 @@ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,clz,csel,rbit,rev,alu_dsp_reg,\ + adr,bfm,bfx,clz,rbit,rev,alu_dsp_reg,\ rotate_imm,shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md index 318b151d646..00574d7930f 100644 --- a/gcc/config/arm/exynos-m1.md +++ b/gcc/config/arm/exynos-m1.md @@ -358,7 +358,7 @@ (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\ alu_sreg, alus_sreg, logic_reg, logics_reg,\ adc_imm, adcs_imm, adc_reg, adcs_reg,\ - adr, bfm, clz, rbit, rev, csel, alu_dsp_reg,\ + adr, bfm, bfx, clz, rbit, rev, csel, alu_dsp_reg,\ shift_imm, shift_reg, rotate_imm, extend,\ mov_imm, mov_reg,\ mvn_imm, mvn_reg,\ @@ -372,7 +372,7 @@ (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\ alu_sreg, alus_sreg, logic_reg, logics_reg,\ adc_imm, adcs_imm, adc_reg, adcs_reg,\ - adr, bfm, clz, rbit, rev, alu_dsp_reg,\ + adr, bfm, bfx, clz, rbit, rev, alu_dsp_reg,\ shift_imm, shift_reg, rotate_imm, extend,\ mov_imm, mov_reg,\ mvn_imm, mvn_reg,\ diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 25f79b4d010..7a95a3704d0 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -51,6 +51,7 @@ ; alus_shift_imm as alu_shift_imm, setting condition flags. ; alus_shift_reg as alu_shift_reg, setting condition flags. ; bfm bitfield move operation. +; bfx bitfield extract operation. ; block blockage insn, this blocks all functional units. ; branch branch. ; call subroutine call. @@ -557,6 +558,7 @@ alus_shift_imm,\ alus_shift_reg,\ bfm,\ + bfx,\ block,\ branch,\ call,\ diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index b7aeac69163..4f27b28461f 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -164,7 +164,7 @@ (define_insn_reservation "xgene1_bfm" 2 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "bfm")) + (eq_attr "type" "bfm,bfx")) "xgene1_decode1op,xgene1_fsu") (define_insn_reservation "xgene1_f_rint" 5