From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 15 Apr 2022 09:45:16 +0000 (+0200)
Subject: Fix reading aiw from other solvers
X-Git-Tag: yosys-0.17~25^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9508bb23303af2571fc146bc0262ec4d70bce4dc;p=yosys.git

Fix reading aiw from other solvers
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index ca4aab566..9c431ab25 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1231,13 +1231,13 @@ struct SimWorker : SimShared
 		{
 			std::string line;
 			std::getline(f, line);
-			if (line.size()==0 || line[0]=='#') continue;
+			if (line.size()==0 || line[0]=='#' || line[0]=='c' || line[0]=='f' || line[0]=='u') continue;
 			if (line[0]=='.') break;
 			if (state==0 && line.size()!=1) {
 				// old format detected, latch data
 				state = 2;
 			}
-			if (state==1 && line[0]!='b' && line[0]!='c') {
+			if (state==1 && line[0]!='b' && line[0]!='j') {
 				// was old format but with 1 bit latch
 				top->setState(latches, status);
 				state = 3;