From: Maurice Becker Date: Tue, 18 Sep 2018 08:27:40 +0000 (+0200) Subject: Pl011: Added registers UART_RSR/UART_ECR X-Git-Tag: v19.0.0.0~1795 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95143897fc9894241c663982496578b67a238be7;p=gem5.git Pl011: Added registers UART_RSR/UART_ECR UART_RSR shows errors with the transmission and UART_ECR can clear those (according to PL011 Technical Reference Manual Revision r1p4). As these transmission errors never occur, they are implemented as RAZ/WI. Both registers exist at the same offset 0x004. RSR is read-only, ECR is write-only. Signed-off-by: Maurice Becker Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02 Reviewed-on: https://gem5-review.googlesource.com/12686 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc index e47cc6753..5ca9f6087 100644 --- a/src/dev/arm/pl011.cc +++ b/src/dev/arm/pl011.cc @@ -92,6 +92,9 @@ Pl011::read(PacketPtr pkt) } } break; + case UART_RSR: + data = 0x0; // We never have errors + break; case UART_FR: data = UART_FR_CTS | // Clear To Send @@ -205,6 +208,8 @@ Pl011::write(PacketPtr pkt) clearInterrupts(UART_TXINTR); raiseInterrupts(UART_TXINTR); break; + case UART_ECR: // clears errors, ignore + break; case UART_CR: control = data; break; diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh index 2317b3114..5a92d8890 100644 --- a/src/dev/arm/pl011.hh +++ b/src/dev/arm/pl011.hh @@ -118,6 +118,8 @@ class Pl011 : public Uart, public AmbaDevice protected: // Registers static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); static const int UART_DR = 0x000; + static const int UART_RSR = 0x004; + static const int UART_ECR = 0x004; static const int UART_FR = 0x018; static const int UART_FR_CTS = 0x001; static const int UART_FR_RXFE = 0x010;