From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 3 May 2022 10:30:23 +0000 (+0100)
Subject: properly fix pagereader.py to parse markdown with indented comments
X-Git-Tag: sv_maxu_works-initial~445
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=953187521903ebe1924a3984fc75e395170fd6c1;p=openpower-isa.git

properly fix pagereader.py to parse markdown with indented comments
these are supposed to be developer-hints rather than actually end up
in the pseudocode itself
---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 7dc9de5e..b4a39fab 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -6,9 +6,9 @@ VA-Form
 
 Pseudo-code:
 
-    # SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    # bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
-    # bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- EXTZ(RC) + prod
     RT <- sum[64:127]
@@ -26,9 +26,9 @@ VA-Form
 
 Pseudo-code:
 
-    # SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    # bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
-    # bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
         dividend[0:(XLEN*2)-1] <- (RC) || (RA)
         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
diff --git a/src/openpower/decoder/pseudo/pagereader.py b/src/openpower/decoder/pseudo/pagereader.py
index c075283b..aa9a0972 100644
--- a/src/openpower/decoder/pseudo/pagereader.py
+++ b/src/openpower/decoder/pseudo/pagereader.py
@@ -144,6 +144,10 @@ class ISA:
             # get pseudocode
             while True:
                 l = lines.pop(0).rstrip()
+                if l.strip().startswith('<!--'):
+                    # print ("skipping comment", l)
+                    l = lines.pop(0).rstrip()  # get first line
+                    continue
                 rewrite.append(l)
                 if len(l) == 0:
                     break
@@ -171,7 +175,7 @@ class ISA:
             while lines:
                 l = lines.pop(0).rstrip()
                 rewrite.append(l)
-                if len(l) != 0 and not l.startswith('<!--'):
+                if len(l) != 0 and not l.strip().startswith('<!--'):
                     break
 
         return rewrite
@@ -198,7 +202,7 @@ class ISA:
             # so please put ending of comments on one line:
             # <!-- line 1 comment -->
             # <!-- line 2 comment -->
-            if l.startswith('<!--'):
+            if l.strip().startswith('<!--'):
                 # print ("skipping comment", l)
                 l = lines.pop(0).rstrip()  # get next line
                 continue
@@ -253,6 +257,8 @@ class ISA:
             li = []
             while True:
                 l = lines.pop(0).rstrip()
+                if l.strip().startswith('<!--'):
+                    continue
                 if len(l) == 0:
                     break
                 assert l.startswith('    '), ("4spcs not found in line %s" % l)
@@ -283,10 +289,10 @@ class ISA:
             for o in opcodes:
                 self.add_op(o, d)
 
-            # expect and drop whitespace
+            # expect and drop whitespace and comments
             while lines:
                 l = lines.pop(0).rstrip()
-                if len(l) != 0 and not l.startswith('<!--'):
+                if len(l) != 0 and not l.strip().startswith('<!--'):
                     break
 
     def add_op(self, o, d):