From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Sat, 16 Apr 2022 18:36:35 +0000 (-0500)
Subject: Revert Microwatt workaround
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95348f69a936ad4dbf02f02f647613d302d3ec14;p=soc.git

Revert Microwatt workaround

The Icache and Dcache controllers are sending
out invalid accesses to Wishbone address space
that is not wired to peripherals, due to a old
Microwat workaround being re-added.

This commit removes the workaround and reenables
the lower address bits, re-aligning the *Cache and
Wishbone address spaces, thus allowing access to
the peripherals.

This partially resolves bug #812
---

diff --git a/src/soc/bus/external_core.py b/src/soc/bus/external_core.py
index 102e66cf..498f9cf3 100644
--- a/src/soc/bus/external_core.py
+++ b/src/soc/bus/external_core.py
@@ -82,11 +82,10 @@ class ExternalCore(Elaboratable):
         # nmigen understands I/O directions (defined by i_ and o_ prefixes)
         ibus, dbus, dmi = self.ibus, self.dbus, self.dmi
 
-        # sigh, microwatt wishbone address is borked, it contains the 3 LSBs
         ibus_adr = Signal(32)
         dbus_adr = Signal(32)
-        m.d.comb += ibus.adr.eq(ibus_adr[3:])
-        m.d.comb += dbus.adr.eq(dbus_adr[3:])
+        m.d.comb += ibus.adr.eq(ibus_adr)
+        m.d.comb += dbus.adr.eq(dbus_adr)
 
         kwargs = {
             # clock/reset signals