From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2019 20:44:39 +0000 (+0200)
Subject: Fix tests/various/async FFL test
X-Git-Tag: working-ls180~1209^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9546ccdbd348b1dc056884a536246801cdf1c4f1;p=yosys.git

Fix tests/various/async FFL test

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index 49ec795d3..4bb4aa047 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -253,6 +253,13 @@ struct Clk2fflogicPass : public Pass {
 						SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
 						Const rstval = cell->parameters["\\ARST_VALUE"];
 
+						Wire *past_arst = module->addWire(NEW_ID);
+						module->addFf(NEW_ID, arst, past_arst);
+						if (cell->parameters["\\ARST_POLARITY"].as_bool())
+							arst = module->LogicOr(NEW_ID, arst, past_arst);
+						else
+							arst = module->LogicAnd(NEW_ID, arst, past_arst);
+
 						if (cell->parameters["\\ARST_POLARITY"].as_bool())
 							module->addMux(NEW_ID, qval, rstval, arst, sig_q);
 						else
diff --git a/tests/various/async.v b/tests/various/async.v
index 1e32a06b5..c27e30c4b 100644
--- a/tests/various/async.v
+++ b/tests/various/async.v
@@ -74,7 +74,7 @@ module testbench;
 			if (q_uut !== q_syn) msg = "SYN";
 			if (q_uut !== q_prp) msg = "PRP";
 			if (q_uut !== q_a2s) msg = "A2S";
-			// if (q_uut !== q_ffl) msg = "FFL";
+			if (q_uut !== q_ffl) msg = "FFL";
 			$display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg);
 			if (msg != "OK") $finish;
 		end