From: Francisco Jerez Date: Thu, 26 Feb 2015 10:56:19 +0000 (+0200) Subject: i965: Pass number of components explicitly to brw_untyped_atomic and _surface_read. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=959d16e38e007b29349d7371fb390a5449c88341;p=mesa.git i965: Pass number of components explicitly to brw_untyped_atomic and _surface_read. And calculate the message response size based on the number of components rather than the other way around. This simplifies their interface somewhat and allows the caller to request a writeback message with more than one vector component in SIMD4x2 mode. Reviewed-by: Topi Pohjolainen Acked-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index a87787eac48..f8fd155c795 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -405,7 +405,7 @@ brw_untyped_atomic(struct brw_compile *p, unsigned atomic_op, unsigned bind_table_index, unsigned msg_length, - unsigned response_length); + bool response_expected); void brw_untyped_surface_read(struct brw_compile *p, @@ -413,7 +413,7 @@ brw_untyped_surface_read(struct brw_compile *p, struct brw_reg mrf, unsigned bind_table_index, unsigned msg_length, - unsigned response_length); + unsigned num_channels); void brw_pixel_interpolator_query(struct brw_compile *p, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 0920e17d3b9..8b134a531b6 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2729,6 +2729,20 @@ brw_svb_write(struct brw_compile *p, send_commit_msg); /* send_commit_msg */ } +static unsigned +brw_surface_payload_size(struct brw_compile *p, + unsigned num_channels, + bool has_simd4x2, + bool has_simd16) +{ + if (has_simd4x2 && brw_inst_access_mode(p->brw, p->current) == BRW_ALIGN_16) + return 1; + else if (has_simd16 && p->compressed) + return 2 * num_channels; + else + return num_channels; +} + static void brw_set_dp_untyped_atomic_message(struct brw_compile *p, brw_inst *insn, @@ -2782,7 +2796,8 @@ brw_untyped_atomic(struct brw_compile *p, unsigned atomic_op, unsigned bind_table_index, unsigned msg_length, - unsigned response_length) { + bool response_expected) +{ const struct brw_context *brw = p->brw; brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND); @@ -2790,7 +2805,9 @@ brw_untyped_atomic(struct brw_compile *p, brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UD)); brw_set_src1(p, insn, brw_imm_d(0)); brw_set_dp_untyped_atomic_message( - p, insn, atomic_op, bind_table_index, msg_length, response_length, + p, insn, atomic_op, bind_table_index, msg_length, + brw_surface_payload_size(p, response_expected, + brw->gen >= 8 || brw->is_haswell, true), brw_inst_access_mode(brw, insn) == BRW_ALIGN_1); } @@ -2800,12 +2817,12 @@ brw_set_dp_untyped_surface_read_message(struct brw_compile *p, unsigned bind_table_index, unsigned msg_length, unsigned response_length, + unsigned num_channels, bool header_present) { const struct brw_context *brw = p->brw; const unsigned dispatch_width = (brw_inst_exec_size(brw, insn) == BRW_EXECUTE_16 ? 16 : 8); - const unsigned num_channels = response_length / (dispatch_width / 8); if (brw->gen >= 8 || brw->is_haswell) { brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1, @@ -2843,7 +2860,7 @@ brw_untyped_surface_read(struct brw_compile *p, struct brw_reg mrf, unsigned bind_table_index, unsigned msg_length, - unsigned response_length) + unsigned num_channels) { const struct brw_context *brw = p->brw; brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); @@ -2851,8 +2868,9 @@ brw_untyped_surface_read(struct brw_compile *p, brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD)); brw_set_src0(p, insn, retype(mrf, BRW_REGISTER_TYPE_UD)); brw_set_dp_untyped_surface_read_message( - p, insn, bind_table_index, msg_length, response_length, - brw_inst_access_mode(brw, insn) == BRW_ALIGN_1); + p, insn, bind_table_index, msg_length, + brw_surface_payload_size(p, num_channels, true, true), + num_channels, brw_inst_access_mode(brw, insn) == BRW_ALIGN_1); } void diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 260f50857b3..bd12147cfed 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1494,8 +1494,9 @@ fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst, surf_index.file == BRW_IMMEDIATE_VALUE && surf_index.type == BRW_REGISTER_TYPE_UD); - brw_untyped_atomic(p, dst, payload, atomic_op.dw1.ud, surf_index.dw1.ud, - inst->mlen, inst->exec_size / 8); + brw_untyped_atomic(p, dst, payload, + atomic_op.dw1.ud, surf_index.dw1.ud, + inst->mlen, true); brw_mark_surface_used(prog_data, surf_index.dw1.ud); } @@ -1508,9 +1509,7 @@ fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst, assert(surf_index.file == BRW_IMMEDIATE_VALUE && surf_index.type == BRW_REGISTER_TYPE_UD); - brw_untyped_surface_read(p, dst, payload, - surf_index.dw1.ud, - inst->mlen, inst->exec_size / 8); + brw_untyped_surface_read(p, dst, payload, surf_index.dw1.ud, inst->mlen, 1); brw_mark_surface_used(prog_data, surf_index.dw1.ud); } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index 2bcddb16286..9714785a48e 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -1125,7 +1125,7 @@ vec4_generator::generate_untyped_atomic(vec4_instruction *inst, brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf), atomic_op.dw1.ud, surf_index.dw1.ud, - inst->mlen, 1); + inst->mlen, true); brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud); } @@ -1139,8 +1139,7 @@ vec4_generator::generate_untyped_surface_read(vec4_instruction *inst, surf_index.type == BRW_REGISTER_TYPE_UD); brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf), - surf_index.dw1.ud, - inst->mlen, 1); + surf_index.dw1.ud, inst->mlen, 1); brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud); }