From: Jordan Justen Date: Tue, 19 Apr 2016 16:34:40 +0000 (-0700) Subject: i965/hsw+: Add support for copying a register X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=959e1e9e6668f9b0e7c480febcaab1e2995fb54b;p=mesa.git i965/hsw+: Add support for copying a register Signed-off-by: Jordan Justen Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index e628564f14a..ba42aa95b09 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1452,6 +1452,8 @@ void brw_store_register_mem32(struct brw_context *brw, drm_intel_bo *bo, uint32_t reg, uint32_t offset); void brw_store_register_mem64(struct brw_context *brw, drm_intel_bo *bo, uint32_t reg, uint32_t offset); +void brw_load_register_reg(struct brw_context *brw, uint32_t src, + uint32_t dest); void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, uint32_t imm); void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo, diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 334be0c427d..33927af2a6a 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -601,6 +601,21 @@ brw_store_register_mem64(struct brw_context *brw, } } +/* + * Copies a 32-bit register. + */ +void +brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest) +{ + assert(brw->gen >= 8 || brw->is_haswell); + + BEGIN_BATCH(3); + OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2)); + OUT_BATCH(src); + OUT_BATCH(dest); + ADVANCE_BATCH(); +} + /* * Write 32-bits of immediate data to a GPU memory buffer. */ diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h index c0d28746875..40931b397a9 100644 --- a/src/mesa/drivers/dri/i965/intel_reg.h +++ b/src/mesa/drivers/dri/i965/intel_reg.h @@ -37,6 +37,7 @@ #define MI_STORE_DATA_IMM (CMD_MI | (0x20 << 23)) #define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23)) +#define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23)) #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2)