From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 01:00:11 +0000 (-0800)
Subject: Only action if there is more than one clock domain
X-Git-Tag: working-ls180~881^2^2~124^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95af8f56e45e23dd29c9a3992f18eee2fa6ceeb1;p=yosys.git

Only action if there is more than one clock domain
---

diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc
index d8d53536d..8f671c175 100644
--- a/passes/techmap/clkpart.cc
+++ b/passes/techmap/clkpart.cc
@@ -233,15 +233,16 @@ struct ClkPartPass : public Pass {
 						std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
 						std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
 
-			for (auto &it : assigned_cells) {
-				RTLIL::Selection sel(false);
-				sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
+			if (assigned_cells.size() > 1)
+				for (auto &it : assigned_cells) {
+					RTLIL::Selection sel(false);
+					sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
 
-				RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
-				Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
+					RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
+					Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
 
-				design->module(submod)->set_bool_attribute(ID(clkpart));
-			}
+					design->module(submod)->set_bool_attribute(ID(clkpart));
+				}
 		}
 	}