From: lkcl <lkcl@web>
Date: Tue, 4 Oct 2022 13:39:05 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~182
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95b73e9ff0b345a4af0a98df3798052da8c24345;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index 48ba0cdb8..c45faed64 100644
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -369,7 +369,7 @@ decision-making, whereas VL=1 will only test the first.
 a need for merging (ORing) all bits into a single alternative predicate mask
 (single-bit) is the sort of thing we can probably live with.
 
-## fast traditional packed SIMD
+## reducing unnecessary setvl interchanges
 
 A major motivation for changing SVP64 with all isvec=0 to temporarily
 override VL to 1 is to allow easy interleaving of Scalar instructions