From: Andrew Jenner Date: Tue, 6 Feb 2018 16:10:43 +0000 (+0000) Subject: powerpcspe.opt: (msimple-fpu, mfpu) Add Undocumented. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95b7eb791371093da660fa88b1d03e6d6a4b9ddd;p=gcc.git powerpcspe.opt: (msimple-fpu, mfpu) Add Undocumented. * config/powerpcspe/powerpcspe.opt: (msimple-fpu, mfpu) Add Undocumented. * config/powerpcspe/sysv4.opt (mbit-align): Likewise. From-SVN: r257417 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f675bbf1b8b..b42a1237140 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-02-06 Andrew Jenner + + * config/powerpcspe/powerpcspe.opt: (msimple-fpu, mfpu) Add + Undocumented. + * config/powerpcspe/sysv4.opt (mbit-align): Likewise. + 2018-02-06 Aldy Hernandez PR tree-optimization/84225 diff --git a/gcc/config/powerpcspe/powerpcspe.opt b/gcc/config/powerpcspe/powerpcspe.opt index 5a1632e9018..79c55bfbf26 100644 --- a/gcc/config/powerpcspe/powerpcspe.opt +++ b/gcc/config/powerpcspe/powerpcspe.opt @@ -516,11 +516,11 @@ Target RejectNegative Var(rs6000_double_float) Save Double-precision floating point unit. msimple-fpu -Target RejectNegative Var(rs6000_simple_fpu) Save +Target Undocumented RejectNegative Var(rs6000_simple_fpu) Save Floating point unit does not support divide & sqrt. mfpu= -Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE) +Target Undocumented RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE) -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu). Enum diff --git a/gcc/config/powerpcspe/sysv4.opt b/gcc/config/powerpcspe/sysv4.opt index 9534c1ce282..b333c4a95b9 100644 --- a/gcc/config/powerpcspe/sysv4.opt +++ b/gcc/config/powerpcspe/sysv4.opt @@ -44,7 +44,7 @@ EnumValue Enum(rs6000_tls_size) String(64) Value(64) mbit-align -Target Report Var(TARGET_NO_BITFIELD_TYPE) Save +Target Undocumented Report Var(TARGET_NO_BITFIELD_TYPE) Save Align to the base type of the bit-field. mstrict-align