From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 06:30:29 +0000 (+0100)
Subject: add images
X-Git-Tag: convert-csv-opcode-to-binary~5310
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95beeecf0311b9d73b24c6cf707b8e0cefff1955;p=libreriscv.git

add images
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index a3fa9161e..993741313 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -96,14 +96,17 @@
 \frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
 
  \begin{itemize}
-   \item memcpy becomes much smaller (higher bang-per-buck)\vspace{10pt}
-   \item context-switch (LOAD/STORE multiple): 1-2 instructions\vspace{10pt}
-   \item Compressed instrs further reduces I-cache (etc.)\vspace{10pt}
-   \item greatly-reduced I-cache load (and less reads)\vspace{10pt}
-  \end{itemize}
-  Note:\vspace{10pt}
+   \item memcpy becomes much smaller (higher bang-per-buck)
+   \item context-switch (LOAD/STORE multiple): 1-2 instructions
+   \item Compressed instrs further reduces I-cache (etc.)
+   \item Greatly-reduced I-cache load (and less reads)
+   \item Amazingly, SIMD becomes (more) tolerable\\
+	     (corner-cases for setup and teardown are gone)
+  \end{itemize}
+  Note:
    \begin{itemize}
    \item It's not just about Vectors: it's about instruction effectiveness
+   \item Anything that makes SIMD tolerable has to be a good thing
    \item Anything implementor is not interested in HW-optimising,\\
 	     let it fall through to exceptions (implement as a trap).
   \end{itemize}