From: Dave Airlie Date: Mon, 5 Jun 2017 03:24:12 +0000 (+1000) Subject: r600: add register info for atomic counters. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95c1e57a18d5b98503b6abee997100c12d6b5b22;p=mesa.git r600: add register info for atomic counters. The atomic counters on evergreen are implemented via append/consume UAV counters. This just adds the register info for them. The EOS packets are used to get the atomic totals extracted post shader execution for storing into a buffer. Reviewed-by: Glenn Kennard --- diff --git a/src/gallium/drivers/r600/eg_sq.h b/src/gallium/drivers/r600/eg_sq.h index e56fdd6d794..935405bbe08 100644 --- a/src/gallium/drivers/r600/eg_sq.h +++ b/src/gallium/drivers/r600/eg_sq.h @@ -540,6 +540,10 @@ #define S_SQ_MEM_GDS_WORD1_DST_REL(x) (((unsigned)(x) & 0x3) << 7) #define S_SQ_MEM_GDS_WORD1_GDS_OP(x) (((unsigned)(x) & 0x3f) << 9) #define S_SQ_MEM_GDS_WORD1_SRC_GPR(x) (((unsigned)(x) & 0x7f) << 16) +#define S_SQ_MEM_GDS_WORD1_UAV_INDEX_MODE(x) (((unsigned)(x) & 0x3) << 24) +#define S_SQ_MEM_GDS_WORD1_UAV_ID(x) (((unsigned)(x) & 0xf) << 26) +#define S_SQ_MEM_GDS_WORD1_ALLOC_CONSUME(x) (((unsigned)(x) & 0x1) << 30) +#define S_SQ_MEM_GDS_WORD1_BCAST_FIRST_REQ(x) (((unsigned)(x) & 0x1) << 31) #define P_SQ_MEM_GDS_WORD2 #define S_SQ_MEM_GDS_WORD2_DST_SEL_X(x) (((unsigned)(x) & 0x7) << 0) diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h index cbcf8018da3..2e54928f08c 100644 --- a/src/gallium/drivers/r600/evergreend.h +++ b/src/gallium/drivers/r600/evergreend.h @@ -50,6 +50,8 @@ #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f #define EVENT_TYPE_VGT_FLUSH 0x24 #define EVENT_TYPE_FLUSH_AND_INV_DB_META 0x2c +#define EVENT_TYPE_CS_DONE 0x2f +#define EVENT_TYPE_PS_DONE 0x30 #define EVENT_TYPE(x) ((x) << 0) #define EVENT_INDEX(x) ((x) << 8) @@ -59,6 +61,7 @@ * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH * 5 - TS events + * 6 - EOS events */ #define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 @@ -96,6 +99,7 @@ #define PKT3_COND_WRITE 0x45 #define PKT3_EVENT_WRITE 0x46 #define PKT3_EVENT_WRITE_EOP 0x47 +#define PKT3_EVENT_WRITE_EOS 0x48 #define PKT3_ONE_REG_WRITE 0x57 #define PKT3_SET_CONFIG_REG 0x68 #define PKT3_SET_CONTEXT_REG 0x69 @@ -164,6 +168,36 @@ #define PKT3_CP_DMA_CMD_SAIC (1 << 28) #define PKT3_CP_DMA_CMD_DAIC (1 << 29) +#define PKT3_SET_APPEND_CNT 0x75 +/* 1. header + * 2. COMMAND + * 1:0 - SOURCE SEL + * 15:2 - Reserved + * 31:16 - WR_REG_OFFSET - context register to write source data to. + * (one of R_02872C_GDS_APPEND_COUNT_0-11) + * 3. CONTROL + * (for source == mem) + * 31:2 SRC_ADDRESS_LO + * 0:1 SWAP + * (for source == GDS) + * 31:0 GDS offset + * (for source == DATA) + * 31:0 DATA + * (for source == REG) + * 31:0 REG + * 4. SRC_ADDRESS_HI[7:0] + * kernel driver 2.44 only supports SRC == MEM. + */ +#define PKT3_SET_APPEND_CNT_SRC_SELECT(x) ((x) << 0) +/* source is from the data in CONTROL */ +#define PKT3_SAC_SRC_SEL_DATA 0x0 +/* source is from register */ +#define PKT3_SAC_SRC_SEL_REG 0x1 +/* source is from GDS offset in CONTROL */ +#define PKT3_SAC_SRC_SEL_GDS 0x2 +/* source is from memory address */ +#define PKT3_SAC_SRC_SEL_MEM 0x3 + /* Registers */ #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC #define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0) @@ -1965,6 +1999,19 @@ #define R_028720_GDS_ADDR_BASE 0x00028720 #define R_028724_GDS_ADDR_SIZE 0x00028724 #define R_028728_GDS_ORDERED_WAVE_PER_SE 0x00028728 +#define R_02872C_GDS_APPEND_COUNT_0 0x0002872C +#define R_028730_GDS_APPEND_COUNT_1 0x00028730 +#define R_028734_GDS_APPEND_COUNT_2 0x00028734 +#define R_028738_GDS_APPEND_COUNT_3 0x00028738 +#define R_02873C_GDS_APPEND_COUNT_4 0x0002873C +#define R_028740_GDS_APPEND_COUNT_5 0x00028740 +#define R_028748_GDS_APPEND_COUNT_6 0x00028744 +#define R_028744_GDS_APPEND_COUNT_7 0x00028748 +#define R_028744_GDS_APPEND_COUNT_8 0x0002874C +#define R_028744_GDS_APPEND_COUNT_9 0x00028750 +#define R_028744_GDS_APPEND_COUNT_10 0x00028754 +#define R_028744_GDS_APPEND_COUNT_11 0x00028758 + #define R_028784_CB_BLEND1_CONTROL 0x00028784 #define R_028788_CB_BLEND2_CONTROL 0x00028788 #define R_02878C_CB_BLEND3_CONTROL 0x0002878C