From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Sep 2020 11:17:34 +0000 (+0100)
Subject: add 3x EINTs to ls180soc
X-Git-Tag: semi_working_ecp5~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95c65d286d17a0aaa4a136b7fd7fd93cdea02a56;p=soc.git

add 3x EINTs to ls180soc
---

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 311e8cfa..dd416ee8 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -2,7 +2,7 @@ import os
 
 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 
-from litex.soc.interconnect import wishbone
+from litex.soc.interconnect import wishbone as wb
 from litex.soc.cores.cpu import CPU
 
 CPU_VARIANTS = ["standard", "standard32"]
@@ -51,19 +51,19 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.interrupt    = Signal(4)
+        self.interrupt    = Signal(16)
 
         if variant == "standard32":
             self.data_width           = 32
-            self.dbus = dbus = wishbone.Interface(data_width=32, adr_width=30)
+            self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
         else:
-            self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
+            self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
             self.data_width           = 64
-        self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
+        self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
 
-        self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=30)
-        self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=30)
-        self.simple_gpio = gpio = wishbone.Interface(data_width=32, adr_width=30)
+        self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
+        self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
+        self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
 
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index f6ee02c1..5b392ef8 100644
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -81,9 +81,13 @@ for i in range(8):
 pinsin = ' '.join(pinsin)
 pinsout = ' '.join(pinsout)
 
+# 8 GPIO in, 8 GPIO out
 _io.append( ("gpio_in", 8, Pins(pinsin), IOStandard("LVCMOS33")) )
 _io.append( ("gpio_out", 8, Pins(pinsout), IOStandard("LVCMOS33")) )
 
+# 3 External INT wires
+_io.append( ("eint", 3, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
+
 # Platform -----------------------------------------------------------------------------------------
 
 class LS180Platform(GenericPlatform):
diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index a00ba5f0..cdbcef13 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -38,20 +38,6 @@ from microwatt import Microwatt
 from litex.soc.integration.soc import SoCCSRHandler
 SoCCSRHandler.supported_address_width.append(12)
 
-# LiteScope IO -------------------------------------------------
-
-class SoCGPIO(Module, AutoCSR):
-    def __init__(self, in_pads, out_pads):
-        self.input  = Signal(len(in_pads))
-        self.output = Signal(len(out_pads))
-
-        # # #
-
-        self.submodules.gpio = GPIOInOut(self.input, self.output)
-
-    def get_csrs(self):
-        return self.gpio.get_csrs()
-
 
 # LibreSoCSim -----------------------------------------------------------------
 
@@ -223,6 +209,8 @@ class LibreSoCSim(SoCCore):
         )
         self.add_csr("spi_master")
 
+        # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins
+        self.comb += self.cpu.interrupt[12:16].eq(platform.request("eint"))
 
         # Debug ---------------------------------------------------------------
         if not debug: