From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 21:58:06 +0000 (-0700)
Subject: synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
X-Git-Tag: working-ls180~1039^2~85
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95db2489bdb515a2e9d3a995574adc8c1071d3c0;p=yosys.git

synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2ac254a1f..b55c40764 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -342,7 +342,10 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_dsp"), "(skip if '-nodsp')") {
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
-				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 "
+						"-D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
 				run("xilinx_dsp");
 				run("chtype -set $mul t:$__soft_mul");
 			}