From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 23:32:14 +0000 (-0700)
Subject: test: add attribute-before-stmt test from @nakengelhardt
X-Git-Tag: working-ls180~538^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95dcd7e785db44fd664fb7d5ac380fa642d0981c;p=yosys.git

test: add attribute-before-stmt test from @nakengelhardt
---

diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys
index eb4f0fac4..4b629ba92 100644
--- a/tests/verilog/bug2037.ys
+++ b/tests/verilog/bug2037.ys
@@ -41,3 +41,18 @@ module test ();
 endmodule
 EOT
 select -assert-none a:*
+
+
+design -reset
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+	reg x = 1'b0;
+	always @(*) begin
+		if (y)
+			(* foo *) x <= 1'b1;
+		else
+			(* bar *) x = 1'b0;
+	end
+endmodule
+EOT