From: Alyssa Rosenzweig Date: Thu, 21 May 2020 16:15:09 +0000 (-0400) Subject: pan/mdg: Add abs/neg/shift modifiers to IR X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95dd478ed325fef8d947f771eae02513725f0f56;p=mesa.git pan/mdg: Add abs/neg/shift modifiers to IR Rather than twiddling them into the ALU packed field. Signed-off-by: Alyssa Rosenzweig Part-of: --- diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h index 1bc93fc441c..cc19b4fb6a1 100644 --- a/src/panfrost/midgard/compiler.h +++ b/src/panfrost/midgard/compiler.h @@ -101,6 +101,21 @@ typedef struct midgard_instruction { nir_alu_type src_types[MIR_SRC_COUNT]; nir_alu_type dest_type; + /* Modifiers, depending on type */ + union { + struct { + bool src_abs[MIR_SRC_COUNT]; + bool src_neg[MIR_SRC_COUNT]; + }; + + struct { + bool src_shift[MIR_SRC_COUNT]; + }; + }; + + /* Out of the union for csel (could maybe be fixed..) */ + bool src_invert[MIR_SRC_COUNT]; + /* Special fields for an ALU instruction */ midgard_reg_info registers; @@ -130,9 +145,6 @@ typedef struct midgard_instruction { uint16_t mask; - /* For accepting ALU ops - invert the nth source */ - bool src_invert[MIR_SRC_COUNT]; - /* Hint for the register allocator not to spill the destination written * from this instruction (because it is a spill/unspill node itself). * Bitmask of spilled classes */ diff --git a/src/panfrost/midgard/mir.c b/src/panfrost/midgard/mir.c index 9651f12bf65..a8d30d3bfef 100644 --- a/src/panfrost/midgard/mir.c +++ b/src/panfrost/midgard/mir.c @@ -444,6 +444,14 @@ mir_flip(midgard_instruction *ins) ins->src_types[0] = ins->src_types[1]; ins->src_types[1] = temp; + temp = ins->src_abs[0]; + ins->src_abs[0] = ins->src_abs[1]; + ins->src_abs[1] = temp; + + temp = ins->src_neg[0]; + ins->src_neg[0] = ins->src_neg[1]; + ins->src_neg[1] = temp; + unsigned temp_swizzle[16]; memcpy(temp_swizzle, ins->swizzle[0], sizeof(ins->swizzle[0])); memcpy(ins->swizzle[0], ins->swizzle[1], sizeof(ins->swizzle[0]));