From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Sep 2019 16:49:15 +0000 (-0700)
Subject: Revert "SigSet<Cell*> to use stable compare class"
X-Git-Tag: working-ls180~1064^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95e80809a5801743fabb2836fa25f3c3732a9a24;p=yosys.git

Revert "SigSet<Cell*> to use stable compare class"

This reverts commit 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.
---

diff --git a/kernel/consteval.h b/kernel/consteval.h
index c1c0c45cc..7a83d28e7 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -33,7 +33,7 @@ struct ConstEval
 	SigMap assign_map;
 	SigMap values_map;
 	SigPool stop_signals;
-	SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver;
+	SigSet<RTLIL::Cell*> sig2driver;
 	std::set<RTLIL::Cell*> busy;
 	std::vector<SigMap> stack;
 	RTLIL::State defaultval;
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index 0a4f9e98d..99f4fbae8 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -116,7 +116,7 @@ struct SccWorker
 		}
 
 		SigPool selectedSignals;
-		SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sigToNextCells;
+		SigSet<RTLIL::Cell*> sigToNextCells;
 
 		for (auto &it : module->wires_)
 			if (design->selected(module, it.second))
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 9850775af..6a8d8cabd 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -37,7 +37,7 @@ struct OptReduceWorker
 	int total_count;
 	bool did_something;
 
-	void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> &drivers, RTLIL::Cell *cell)
+	void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*> &drivers, RTLIL::Cell *cell)
 	{
 		if (cells.count(cell) == 0)
 			return;
@@ -289,7 +289,7 @@ struct OptReduceWorker
 			const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
 			for (auto type : type_list)
 			{
-				SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> drivers;
+				SigSet<RTLIL::Cell*> drivers;
 				pool<RTLIL::Cell*> cells;
 
 				for (auto &cell_it : module->cells_) {
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 8d4b6b14b..0bf74098a 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -29,7 +29,7 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 SigMap assign_map, dff_init_map;
-SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> mux_drivers;
+SigSet<RTLIL::Cell*> mux_drivers;
 dict<SigBit, RTLIL::Cell*> bit2driver;
 dict<SigBit, pool<SigBit>> init_attributes;
 
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 097fc5a2e..430bba1e8 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -61,7 +61,7 @@ struct SatHelper
 	// model variables
 	std::vector<std::string> shows;
 	SigPool show_signal_pool;
-	SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> show_drivers;
+	SigSet<RTLIL::Cell*> show_drivers;
 	int max_timestep, timeout;
 	bool gotTimeout;