From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Jul 2020 14:04:43 +0000 (+0100)
Subject: add option to generate verilog
X-Git-Tag: semi_working_ecp5~687
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95eed9f8c85aaca0f913abb6f752391f92d5ec84;p=soc.git

add option to generate verilog
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 3f7ed3a7..5e88deaf 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -17,6 +17,8 @@ improved.
 
 from nmigen import Elaboratable, Module, Signal
 from nmigen.cli import rtlil
+from nmigen.cli import main
+import sys
 
 from soc.decoder.decode2execute1 import Data
 from soc.experiment.testmem import TestMemory # test only for instructions
@@ -197,7 +199,9 @@ if __name__ == '__main__':
                          reg_wid=64,
                          units=units)
     dut = TestIssuer(pspec)
-    vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
-    with open("test_issuer.il", "w") as f:
-        f.write(vl)
+    vl = main(dut, ports=dut.ports(), name="test_issuer")
 
+    if len(sys.argv) == 1:
+        vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
+        with open("test_issuer.il", "w") as f:
+            f.write(vl)