From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 20:44:41 +0000 (-0700)
Subject: Update doc
X-Git-Tag: working-ls180~1039^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95f0dd57df5209f77df6771e381b87871ab9860a;p=yosys.git

Update doc
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index b0251de50..5ccc47ba8 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -578,7 +578,8 @@ struct XilinxDspPass : public Pass {
 		log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
 		log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n");
 		log("input to the post-adder -- a pattern common for summing partial products to\n");
-		log("implement wide multipliers).\n");
+		log("implement wide multipliers). Initial support also exists for similar cascading\n");
+		log("for AREG and BREG using '[AB]OUT' -> '[AB]IN'.\n");
 		log("\n");
 		log("\n");
 		log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");