From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Apr 2021 10:48:42 +0000 (+0000)
Subject: back to "working" verilog add
X-Git-Tag: LS180_RC3~134
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9610fba9110f85e497019f915f5f7e4caab1380d;p=soclayout.git

back to "working" verilog add
---

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index 7cbabb9..33311d3 100644
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -20,10 +20,10 @@ class ADD(Elaboratable):
 
         # set up JTAG
         self.jtag = TAP(ir_width=4)
-        self.jtag.bus.tck.name = 'jtag_tck'
-        self.jtag.bus.tms.name = 'jtag_tms'
-        self.jtag.bus.tdo.name = 'jtag_tdo'
-        self.jtag.bus.tdi.name = 'jtag_tdi'
+        self.jtag.bus.tck.name = 'tck'
+        self.jtag.bus.tms.name = 'tms'
+        self.jtag.bus.tdo.name = 'tdo'
+        self.jtag.bus.tdi.name = 'tdi'
 
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
@@ -50,7 +50,8 @@ def create_verilog(dut, ports, test_name):
         f.write(vl)
 
 if __name__ == "__main__":
-    alu = DomainRenamer("sys")(ADD(width=4))
+    #alu = DomainRenamer("sys")(ADD(width=4))
+    alu = (ADD(width=4))
     create_verilog(alu, [alu.a, alu.b, alu.f,
                        alu.jtag.bus.tck,
                         alu.jtag.bus.tms,
diff --git a/experiments10_verilog/coriolis2/settings.py b/experiments10_verilog/coriolis2/settings.py
index 22c9c85..7c24dff 100644
--- a/experiments10_verilog/coriolis2/settings.py
+++ b/experiments10_verilog/coriolis2/settings.py
@@ -35,7 +35,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
     af  = CRL.AllianceFramework.get()
     env = af.getEnvironment()
-    env.setCLOCK( '^sys_clk|^ck|^tck' )
+    env.setCLOCK( '^clk|^ck|^tck' )
     env.setPOWER( 'vdd' )
     env.setGROUND( 'vss' )
     env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib',
diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index 26df5bd..addccdb 100644
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -42,18 +42,18 @@ def scriptMain ( **kw ):
          , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
          , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'     )
          , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'     )
-         , (IoPin.EAST , None, 'p_tms_0'    , 'jtag_tms'    , 'jtag_tms'      )
-         , (IoPin.EAST , None, 'p_tdo_0'    , 'jtag_tdo'    , 'jtag_tdo'      )
+         , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'      )
+         , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'      )
          , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
-         , (IoPin.EAST , None, 'p_sys_clk'  , 'sys_clk'    , 'sys_clk'      )
-         , (IoPin.EAST , None, 'p_tck'      , 'jtag_tck'    , 'jtag_tck'      )
-         , (IoPin.EAST , None, 'p_tdi_0'    , 'jtag_tdi'    , 'jtag_tdi'      )
+         , (IoPin.EAST , None, 'clk'  , 'clk'    , 'clk'      )
+         , (IoPin.EAST , None, 'p_tck'      , 'tck'    , 'tck'      )
+         , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'      )
          , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'     )
          , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
          , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
          , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
          , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'     )
-         , (IoPin.NORTH, None, 'p_sys_rst'  , 'sys_rst'    , 'sys_rst'      )
+         , (IoPin.NORTH, None, 'rst'  , 'rst'    , 'rst'      )
          , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'     )
          , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'     )
          , (IoPin.WEST , None, 'power_1'    , 'vdd'    )