From: lkcl <lkcl@web>
Date: Thu, 24 Dec 2020 06:31:28 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~977
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96480534a90e1bc7c17163e352c3bc5af6fc8174;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index e3c818f67..b51923fa7 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -19,6 +19,8 @@ The fundamentals are:
 * Some registers may be "tagged" as Vectors
 * During the loop, "Vector"-tagged register are incrememted by
   one with each iteration.
+* Once the loop is completed *only then* is the Program Counter
+  allowed to move to the next instruction.
 
 In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both source and destination have been "tagged" as Vectors, is simply: