From: lkcl <lkcl@web>
Date: Wed, 4 Aug 2021 15:11:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~499
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9654d3951d5944f7739c9ee556aa9a5c3c4af2f1;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 7ec90552a..7d9b73414 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -148,7 +148,8 @@ Available options to combine:
 In addition to the above, it is necessary to select whether, in `svstep`
 mode, the Vector CR Field is to be overwritten or not: in some cases
 it is useful to know but in others all that is needed is the branch itself.
-In the case of `sv.bc` there is no additional bitspace so the ``AA`
+In the case of `sv.bc` there is no additional bitspace, so on the
+basis that it is rarely used, the `AA`
 field is re-interpreted instead to be `Rc`. For `sv.bclr`, there is free
 bitspace and so bit 16 has been chosen as `Rc`.