From: Jean THOMAS Date: Wed, 10 Jun 2020 13:51:21 +0000 (+0200) Subject: Remove unused files X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96660a8722a26a0e73cdfa8aa89a7b51a00adf32;p=gram.git Remove unused files --- diff --git a/gram/frontend/bist.py b/gram/frontend/bist.py deleted file mode 100644 index 8dbd1d7..0000000 --- a/gram/frontend/bist.py +++ /dev/null @@ -1,786 +0,0 @@ -# This file is Copyright (c) 2016-2019 Florent Kermarrec -# This file is Copyright (c) 2016 Tim 'mithro' Ansell -# License: BSD - -"""Built In Self Test (BIST) modules for testing LiteDRAM functionality.""" - -from functools import reduce -from operator import xor - -from migen import * - -from litex.soc.interconnect import stream -from litex.soc.interconnect.csr import * - -from litedram.common import LiteDRAMNativePort -from litedram.frontend.axi import LiteDRAMAXIPort -from litedram.frontend.dma import LiteDRAMDMAWriter, LiteDRAMDMAReader - -# LFSR --------------------------------------------------------------------------------------------- - - -class LFSR(Module): - """Linear-Feedback Shift Register to generate a pseudo-random sequence. - - Parameters - ---------- - n_out : int - Width of the output data signal. - n_state : int - LFSR internal state - taps : list of int - LFSR taps (from polynom) - - Attributes - ---------- - o : out - Output data - """ - - def __init__(self, n_out, n_state, taps): - self.o = Signal(n_out) - - # # # - - state = Signal(n_state) - curval = [state[i] for i in range(n_state)] - curval += [0]*(n_out - n_state) - for i in range(n_out): - nv = ~reduce(xor, [curval[tap] for tap in taps]) - curval.insert(0, nv) - curval.pop() - - self.sync += [ - state.eq(Cat(*curval[:n_state])), - self.o.eq(Cat(*curval)) - ] - -# Counter ------------------------------------------------------------------------------------------ - - -class Counter(Module): - """Simple incremental counter. - - Parameters - ---------- - n_out : int - Width of the output data signal. - - Attributes - ---------- - o : out - Output data - """ - - def __init__(self, n_out): - self.o = Signal(n_out) - - # # # - - self.sync += self.o.eq(self.o + 1) - -# Generator ---------------------------------------------------------------------------------------- - - -@CEInserter() -class Generator(Module): - """Address/Data Generator. - - Parameters - ---------- - n_out : int - Width of the output data signal. - - Attributes - ---------- - random_enable : in - Enable Random (LFSR) - - o : out - Output data - """ - - def __init__(self, n_out, n_state, taps): - self.random_enable = Signal() - self.o = Signal(n_out) - - # # # - - lfsr = LFSR(n_out, n_state, taps) - count = Counter(n_out) - self.submodules += lfsr, count - - self.comb += \ - If(self.random_enable, - self.o.eq(lfsr.o) - ).Else( - self.o.eq(count.o) - ) - - -def get_ashift_awidth(dram_port): - if isinstance(dram_port, LiteDRAMNativePort): - ashift = log2_int(dram_port.data_width//8) - awidth = dram_port.address_width + ashift - elif isinstance(dram_port, LiteDRAMAXIPort): - ashift = log2_int(dram_port.data_width//8) - awidth = dram_port.address_width - else: - raise NotImplementedError - return ashift, awidth - -# _LiteDRAMBISTGenerator --------------------------------------------------------------------------- - - -@ResetInserter() -class _LiteDRAMBISTGenerator(Module): - def __init__(self, dram_port): - ashift, awidth = get_ashift_awidth(dram_port) - self.start = Signal() - self.done = Signal() - self.base = Signal(awidth) - self.end = Signal(awidth) - self.length = Signal(awidth) - self.random_data = Signal() - self.random_addr = Signal() - self.ticks = Signal(32) - - self.run_cascade_in = Signal(reset=1) - self.run_cascade_out = Signal() - - # # # - - # Data / Address generators ---------------------------------------------------------------- - data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31 - addr_gen = Generator(31, n_state=31, taps=[27, 30]) - self.submodules += data_gen, addr_gen - self.comb += data_gen.random_enable.eq(self.random_data) - self.comb += addr_gen.random_enable.eq(self.random_addr) - - # mask random address to the range -# This file is Copyright (c) 2016-2019 Florent Kermarrec -# This file is Copyright (c) 2018 John Sully -# This file is Copyright (c) 2016 Tim 'mithro' Ansell -# License: BSD - -"""Direct Memory Access (DMA) reader and writer modules.""" - -from migen import * - -from litex.soc.interconnect.csr import * -from litex.soc.interconnect import stream - -from litedram.common import LiteDRAMNativePort -from litedram.frontend.axi import LiteDRAMAXIPort - -# LiteDRAMDMAReader -------------------------------------------------------------------------------- - - -class LiteDRAMDMAReader(Module, AutoCSR): - """Read data from DRAM memory. - - For every address written to the sink, one DRAM word will be produced on - the source. - - Parameters - ---------- - port : port - Port on the DRAM memory controller to read from (Native or AXI). - - fifo_depth : int - How many request results the output FIFO can contain (and thus how many - read requests can be outstanding at once). - - fifo_buffered : bool - Implement FIFO in Block Ram. - - Attributes - ---------- - sink : Record("address") - Sink for DRAM addresses to be read. - - source : Record("data") - Source for DRAM word results from reading. - - rsv_level: Signal() - FIFO reservation level counter - """ - - def __init__(self, port, fifo_depth=16, fifo_buffered=False): - assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort)) - self.port = port - self.sink = sink = stream.Endpoint([("address", port.address_width)]) - self.source = source = stream.Endpoint([("data", port.data_width)]) - - # # # - - # Native / AXI selection - is_native = isinstance(port, LiteDRAMNativePort) - is_axi = isinstance(port, LiteDRAMAXIPort) - if is_native: - (cmd, rdata) = port.cmd, port.rdata - elif is_axi: - (cmd, rdata) = port.ar, port.r - else: - raise NotImplementedError - - # Request issuance ------------------------------------------------------------------------- - request_enable = Signal() - request_issued = Signal() - - if is_native: - self.comb += cmd.we.eq(0) - self.comb += [ - cmd.addr.eq(sink.address), - cmd.valid.eq(sink.valid & request_enable), - sink.ready.eq(cmd.ready & request_enable), - request_issued.eq(cmd.valid & cmd.ready) - ] - - # FIFO reservation level counter ----------------------------------------------------------- - # incremented when data is planned to be queued - # decremented when data is dequeued - data_dequeued = Signal() - self.rsv_level = rsv_level = Signal(max=fifo_depth+1) - self.sync += [ - If(request_issued, - If(~data_dequeued, rsv_level.eq(self.rsv_level + 1)) - ).Elif(data_dequeued, - rsv_level.eq(rsv_level - 1) - ) - ] - self.comb += request_enable.eq(rsv_level != fifo_depth) - - # FIFO ------------------------------------------------------------------------------------- - fifo = stream.SyncFIFO( - [("data", port.data_width)], fifo_depth, fifo_buffered) - self.submodules += fifo - - self.comb += [ - rdata.connect(fifo.sink, omit={"id", "resp"}), - fifo.source.connect(source), - data_dequeued.eq(source.valid & source.ready) - ] - - def add_csr(self): - self._base = CSRStorage(32) - self._length = CSRStorage(32) - self._start = CSR() - self._done = CSRStatus() - self._loop = CSRStorage() - - # # # - - shift = log2_int(self.port.data_width//8) - base = Signal(self.port.address_width) - offset = Signal(self.port.address_width) - length = Signal(self.port.address_width) - self.comb += [ - base.eq(self._base.storage[shift:]), - length.eq(self._length.storage[shift:]), - ] - - self.submodules.fsm = fsm = FSM(reset_state="IDLE") - fsm.act("IDLE", - self._done.status.eq(1), - If(self._start.re, - NextValue(offset, 0), - NextState("RUN"), - ) - ) - fsm.act("RUN", - self.sink.valid.eq(1), - self.sink.address.eq(base + offset), - If(self.sink.ready, - NextValue(offset, offset + 1), - If(offset == (length - 1), - If(self._loop.storage, - NextValue(offset, 0) - ).Else( - NextState("IDLE") - ) - ) - ) - ) - -# LiteDRAMDMAWriter -------------------------------------------------------------------------------- - - -class LiteDRAMDMAWriter(Module, AutoCSR): - """Write data to DRAM memory. - - Parameters - ---------- - port : port - Port on the DRAM memory controller to write to (Native or AXI). - - fifo_depth : int - How many requests the input FIFO can contain (and thus how many write - requests can be outstanding at once). - - fifo_buffered : bool - Implement FIFO in Block Ram. - - Attributes - ---------- - sink : Record("address", "data") - Sink for DRAM addresses and DRAM data word to be written too. - """ - - def __init__(self, port, fifo_depth=16, fifo_buffered=False): - assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort)) - self.port = port - self.sink = sink = stream.Endpoint([("address", port.address_width), - ("data", port.data_width)]) - - # # # - - # Native / AXI selection ------------------------------------------------------------------- - is_native = isinstance(port, LiteDRAMNativePort) - is_axi = isinstance(port, LiteDRAMAXIPort) - if is_native: - (cmd, wdata) = port.cmd, port.wdata - elif is_axi: - (cmd, wdata) = port.aw, port.w - else: - raise NotImplementedError - - # FIFO ------------------------------------------------------------------------------------- - fifo = stream.SyncFIFO( - [("data", port.data_width)], fifo_depth, fifo_buffered) - self.submodules += fifo - - if is_native: - self.comb += cmd.we.eq(1) - self.comb += [ - cmd.addr.eq(sink.address), - cmd.valid.eq(fifo.sink.ready & sink.valid), - sink.ready.eq(fifo.sink.ready & cmd.ready), - fifo.sink.valid.eq(sink.valid & cmd.ready), - fifo.sink.data.eq(sink.data) - ] - - if is_native: - self.comb += wdata.we.eq(2**(port.data_width//8)-1) - if is_axi: - self.comb += wdata.strb.eq(2**(port.data_width//8)-1) - self.comb += [ - wdata.valid.eq(fifo.source.valid), - fifo.source.ready.eq(wdata.ready), - wdata.data.eq(fifo.source.data) - ] - - def add_csr(self): - self._sink = self.sink - self.sink = stream.Endpoint([("data", self.port.data_width)]) - - self._base = CSRStorage(32) - self._length = CSRStorage(32) - self._start = CSR() - self._done = CSRStatus() - self._loop = CSRStorage() - - # # # - - shift = log2_int(self.port.data_width//8) - base = Signal(self.port.address_width) - offset = Signal(self.port.address_width) - length = Signal(self.port.address_width) - self.comb += [ - base.eq(self._base.storage[shift:]), - length.eq(self._length.storage[shift:]), - ] - - self.submodules.fsm = fsm = FSM(reset_state="IDLE") - fsm.act("IDLE", - self._done.status.eq(1), - If(self._start.re, - NextValue(offset, 0), - NextState("RUN"), - ) - ) - fsm.act("RUN", - self._sink.valid.eq(self.sink.valid), - self._sink.data.eq(self.sink.data), - self._sink.address.eq(base + offset), - self.sink.ready.eq(self._sink.ready), - If(self.sink.valid & self.sink.ready, - NextValue(offset, offset + 1), - If(offset == (length - 1), - If(self._loop.storage, - NextValue(offset, 0) - ).Else( - NextState("IDLE") - ) - ) - ) - ) diff --git a/gram/frontend/ecc.py b/gram/frontend/ecc.py deleted file mode 100644 index 59dc279..0000000 --- a/gram/frontend/ecc.py +++ /dev/null @@ -1,150 +0,0 @@ -# This file is Copyright (c) 2018-2019 Florent Kermarrec -# License: BSD - -""" -ECC frontend for LiteDRAM - -Adds ECC support to Native ports. - -Features: -- Single Error Correction. -- Double Error Detection. -- Errors injection. -- Errors reporting. - -Limitations: -- Byte enable not supported for writes. -""" - -from migen import * - -from litex.soc.interconnect.csr import * -from litex.soc.interconnect.stream import * -from litex.soc.cores.ecc import * - -from litedram.common import wdata_description, rdata_description - - -# LiteDRAMNativePortECCW --------------------------------------------------------------------------- - -class LiteDRAMNativePortECCW(Module): - def __init__(self, data_width_from, data_width_to): - self.sink = sink = Endpoint(wdata_description(data_width_from)) - self.source = source = Endpoint(wdata_description(data_width_to)) - - # # # - - for i in range(8): - encoder = ECCEncoder(data_width_from//8) - self.submodules += encoder - self.comb += [ - sink.connect(source, omit={"data", "we"}), - encoder.i.eq(sink.data[i*data_width_from // - 8:(i+1)*data_width_from//8]), - source.data[i*data_width_to // - 8:(i+1)*data_width_to//8].eq(encoder.o) - ] - self.comb += source.we.eq(2**len(source.we)-1) - -# LiteDRAMNativePortECCR --------------------------------------------------------------------------- - - -class LiteDRAMNativePortECCR(Module): - def __init__(self, data_width_from, data_width_to): - self.sink = sink = Endpoint(rdata_description(data_width_to)) - self.source = source = Endpoint(rdata_description(data_width_from)) - self.enable = Signal() - self.sec = Signal(8) - self.ded = Signal(8) - - # # # - - self.comb += sink.connect(source, omit={"data"}) - - for i in range(8): - decoder = ECCDecoder(data_width_from//8) - self.submodules += decoder - self.comb += [ - decoder.enable.eq(self.enable), - decoder.i.eq(sink.data[i*data_width_to // - 8:(i+1)*data_width_to//8]), - source.data[i*data_width_from // - 8:(i+1)*data_width_from//8].eq(decoder.o), - If(source.valid, - self.sec[i].eq(decoder.sec), - self.ded[i].eq(decoder.ded) - ) - ] - -# LiteDRAMNativePortECC ---------------------------------------------------------------------------- - - -class LiteDRAMNativePortECC(Module, AutoCSR): - def __init__(self, port_from, port_to, with_error_injection=False): - _, n = compute_m_n(port_from.data_width//8) - assert port_to.data_width >= (n + 1)*8 - - self.enable = CSRStorage(reset=1) - self.clear = CSR() - self.sec_errors = CSRStatus(32) - self.ded_errors = CSRStatus(32) - self.sec_detected = sec_detected = Signal() - self.ded_detected = ded_detected = Signal() - if with_error_injection: - self.flip = CSRStorage(8) - - # # # - - # Cmd -------------------------------------------------------------------------------------- - self.comb += port_from.cmd.connect(port_to.cmd) - - # Wdata (ecc encoding) --------------------------------------------------------------------- - ecc_wdata = LiteDRAMNativePortECCW( - port_from.data_width, port_to.data_width) - ecc_wdata = BufferizeEndpoints({"source": DIR_SOURCE})(ecc_wdata) - self.submodules += ecc_wdata - self.comb += [ - port_from.wdata.connect(ecc_wdata.sink), - ecc_wdata.source.connect(port_to.wdata) - ] - if with_error_injection: - self.comb += port_to.wdata.data[:8].eq( - self.flip.storage ^ ecc_wdata.source.data[:8]) - - # Rdata (ecc decoding) --------------------------------------------------------------------- - sec = Signal() - ded = Signal() - ecc_rdata = LiteDRAMNativePortECCR( - port_from.data_width, port_to.data_width) - ecc_rdata = BufferizeEndpoints({"source": DIR_SOURCE})(ecc_rdata) - self.submodules += ecc_rdata - self.comb += [ - ecc_rdata.enable.eq(self.enable.storage), - port_to.rdata.connect(ecc_rdata.sink), - ecc_rdata.source.connect(port_from.rdata) - ] - - # Errors count ----------------------------------------------------------------------------- - sec_errors = self.sec_errors.status - ded_errors = self.ded_errors.status - self.sync += [ - If(self.clear.re, - sec_errors.eq(0), - ded_errors.eq(0), - sec_detected.eq(0), - ded_detected.eq(0), - ).Else( - If(sec_errors != (2**len(sec_errors) - 1), - If(ecc_rdata.sec != 0, - sec_detected.eq(1), - sec_errors.eq(sec_errors + 1) - ) - ), - If(ded_errors != (2**len(ded_errors) - 1), - If(ecc_rdata.ded != 0, - ded_detected.eq(1), - ded_errors.eq(ded_errors + 1) - ) - ) - ) - ] diff --git a/gram/frontend/fifo.py b/gram/frontend/fifo.py deleted file mode 100644 index 5fac460..0000000 --- a/gram/frontend/fifo.py +++ /dev/null @@ -1,127 +0,0 @@ -# This file is Copyright (c) 2018-2019 Florent Kermarrec -# License: BSD - -from nmigen import * -#from litex.gen import * - -#from litex.soc.interconnect import stream - -#from litedram.frontend import dma - - -def _inc(signal, modulo): - if modulo == 2**len(signal): - return signal.eq(signal + 1) - else: - return If(signal == (modulo - 1), - signal.eq(0) - ).Else( - signal.eq(signal + 1) - ) - - -class _LiteDRAMFIFOCtrl(Module): - def __init__(self, base, depth, read_threshold, write_threshold): - self.base = base - self.depth = depth - self.level = Signal(max=depth+1) - - # # # - - # To write buffer - self.writable = Signal() - self.write_address = Signal(max=depth) - - # From write buffer - self.write = Signal() - - # To read buffer - self.readable = Signal() - self.read_address = Signal(max=depth) - - # From read buffer - self.read = Signal() - - def elaborate(self, platform): - m = Module() - - produce = self.write_address - consume = self.read_address - - with m.If(self.write): - m.d.sync += _inc(produce, depth) - with m.If(~self.read): - m.d.sync += self.level.eq(self.level + 1) - with m.If(self.read): - m.d.sync += _inc(consume, depth) - with m.If(~self.write): - m.d.sync += self.level.eq(self.level - 1) - - m.d.comb += [ - self.writable.eq(self.level < write_threshold), - self.readable.eq(self.level > read_threshold) - ] - - return m - - -class _LiteDRAMFIFOWriter(Module): - def __init__(self, data_width, port, ctrl): - self.sink = sink = stream.Endpoint([("data", data_width)]) - - # # # - - self.submodules.writer = writer = dma.LiteDRAMDMAWriter( - port, fifo_depth=32) - self.comb += [ - writer.sink.valid.eq(sink.valid & ctrl.writable), - writer.sink.address.eq(ctrl.base + ctrl.write_address), - writer.sink.data.eq(sink.data), - If(writer.sink.valid & writer.sink.ready, - ctrl.write.eq(1), - sink.ready.eq(1) - ) - ] - - -class _LiteDRAMFIFOReader(Module): - def __init__(self, data_width, port, ctrl): - self.source = source = stream.Endpoint([("data", data_width)]) - - # # # - - self.submodules.reader = reader = dma.LiteDRAMDMAReader( - port, fifo_depth=32) - self.comb += [ - reader.sink.valid.eq(ctrl.readable), - reader.sink.address.eq(ctrl.base + ctrl.read_address), - If(reader.sink.valid & reader.sink.ready, - ctrl.read.eq(1) - ) - ] - self.comb += reader.source.connect(source) - - -class LiteDRAMFIFO(Module): - def __init__(self, data_width, base, depth, write_port, read_port, - read_threshold=None, write_threshold=None): - self.sink = stream.Endpoint([("data", data_width)]) - self.source = stream.Endpoint([("data", data_width)]) - - # # # - - if read_threshold is None: - read_threshold = 0 - if write_threshold is None: - write_threshold = depth - - self.submodules.ctrl = _LiteDRAMFIFOCtrl( - base, depth, read_threshold, write_threshold) - self.submodules.writer = _LiteDRAMFIFOWriter( - data_width, write_port, self.ctrl) - self.submodules.reader = _LiteDRAMFIFOReader( - data_width, read_port, self.ctrl) - self.comb += [ - self.sink.connect(self.writer.sink), - self.reader.source.connect(self.source) - ]