From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 26 Feb 2019 02:40:53 +0000 (-0800)
Subject: abc9 cleanup
X-Git-Tag: working-ls180~1237^2~257
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=967297cd57f80f0b55f7e1d1e00fd6c20b8fb52a;p=yosys.git

abc9 cleanup
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 68e54f518..de47de92e 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -892,21 +892,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			}
 			log_assert(GetSize(signal) >= GetSize(remap_wire));
 
+			log_assert(w->port_input || w->port_output);
+			RTLIL::SigSig conn;
 			if (w->port_input) {
-				RTLIL::SigSig conn;
 				conn.first = remap_wire;
 				conn.second = signal;
 				in_wires++;
-				module->connect(conn);
 			}
-			else if (w->port_output) {
-				RTLIL::SigSig conn;
+			if (w->port_output) {
 				conn.first = signal;
 				conn.second = remap_wire;
 				out_wires++;
-				module->connect(conn);
 			}
-			else log_abort();
+			module->connect(conn);
 		}
 
 		//log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);