From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 19 Jan 2024 07:15:38 +0000 (-0800)
Subject: add SVP64 intro page
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9673fc399438a30e3bcc1e4feaef981ba261a08d;p=libreriscv.git

add SVP64 intro page
---

diff --git a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
index f9b8d43bc..948e80cdb 100644
--- a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
+++ b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
@@ -22,6 +22,27 @@
     \titlepage
 \end{frame}
 
+\begin{frame}[fragile]
+    \frametitle{What is SVP64?}
+    \begin{itemize}
+        \item Vectorization Extension to PowerISA developed by Libre-SOC
+        \pause
+        \item Basically, a way to modify nearly any PowerISA instruction to run it in a HW loop.
+        \pause \\
+        \medskip
+        Simple Example:
+        \begin{semiverbatim}
+# let's assume VL was previously set to 3
+sv.add *r3, *r15, r12  # adds 3 times
+\pause
+# expands to:
+add r3, r15, r12  \only<+(1)->{# no * means r12 doesn't increment}
+add r4, r16, r12  \only<+(1)->{# * means r3 and r15 increment}
+add r5, r17, r12
+        \end{semiverbatim}
+    \end{itemize}
+\end{frame}
+
 \begin{frame}
     \input{test.dia-tex}
 \end{frame}