From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 1 Mar 2019 22:14:02 +0000 (+0000)
Subject: pass add0 z through to add1 independently
X-Git-Tag: ls180-24jan2020~1783
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96a14ea216c0496f839b3a4186516bd515d6f3c6;p=ieee754fpu.git

pass add0 z through to add1 independently
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 2e3dadf4..9380bb8e 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -481,7 +481,7 @@ class FPAddStage1Mod(FPState):
         """
         m.d.comb += self.in_z.copy(in_z)
         m.d.comb += self.in_tot.eq(in_tot)
-        m.d.comb += out_z.copy(self.out_z)
+        #m.d.comb += out_z.copy(self.out_z)
         #m.d.comb += out_of.copy(self.out_of)
 
     def elaborate(self, platform):
@@ -524,7 +524,7 @@ class FPAddStage1(FPState):
     def action(self, m):
         m.submodules.add1_out_overflow = self.out_of
         m.d.sync += self.out_of.copy(self.mod.out_of)
-        m.d.sync += self.z.copy(self.out_z)
+        m.d.sync += self.out_z.copy(self.mod.out_z)
         m.next = "normalise_1"
 
 
@@ -778,20 +778,22 @@ class FPADD:
             alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
         m.submodules.align = alm.mod
 
-        az = FPNumOut(self.width, False)
-        m.submodules.fpnum_az = az
+        az1 = FPNumOut(self.width, False)
+        m.submodules.fpnum_az1 = az1
 
         add0 = self.add_state(FPAddStage0(self.width))
         add0.set_inputs({"a": alm.out_a, "b": alm.out_b})
-        add0.set_outputs({"z": az})
-        add0.mod.setup(m, alm.out_a, alm.out_b, az, add0.out_z, add0.out_tot)
+        add0.set_outputs({"z": az1})
+        add0.mod.setup(m, alm.out_a, alm.out_b, az1, add0.out_z, add0.out_tot)
         m.submodules.add0 = add0.mod
 
         add1 = self.add_state(FPAddStage1(self.width))
-        add1.set_outputs({"z": az})  # XXX Z as output
-        add1.mod.setup(m, add0.out_tot, az, add1.out_z, add1.out_of)
+        #add1.set_outputs({"z": az})  # XXX Z as output
+        add1.mod.setup(m, add0.out_tot, az1, None, add1.out_of)
         m.submodules.add1 = add1.mod
 
+        az = add1.out_z
+
         of = add1.out_of
 
         n1 = self.add_state(FPNorm1(self.width))