From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Dec 2017 20:48:31 +0000 (+0100)
Subject: Add SigSpec::is_fully_ones()
X-Git-Tag: yosys-0.8~252
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96ad6888496f4cd34bbf461ce26f97f598bf898c;p=yosys.git

Add SigSpec::is_fully_ones()
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8c3d2962c..7dc7107c1 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3353,6 +3353,21 @@ bool RTLIL::SigSpec::is_fully_zero() const
 	return true;
 }
 
+bool RTLIL::SigSpec::is_fully_ones() const
+{
+	cover("kernel.rtlil.sigspec.is_fully_ones");
+
+	pack();
+	for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
+		if (it->width > 0 && it->wire != NULL)
+			return false;
+		for (size_t i = 0; i < it->data.size(); i++)
+			if (it->data[i] != RTLIL::State::S1)
+				return false;
+	}
+	return true;
+}
+
 bool RTLIL::SigSpec::is_fully_def() const
 {
 	cover("kernel.rtlil.sigspec.is_fully_def");
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6ce9b6748..b33cb53a3 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -704,6 +704,7 @@ public:
 
 	bool is_fully_const() const;
 	bool is_fully_zero() const;
+	bool is_fully_ones() const;
 	bool is_fully_def() const;
 	bool is_fully_undef() const;
 	bool has_const() const;